Implementation of area optimization precoder in a 40 Gb/s PolDM-DQPSK system-中国Betway体育网页登陆

摘要 Inthispaper,anewmodelbasedonanimprovedBrentKung(BK)parallelprefixnetwork(PPN)algorithmisproposedandrealizedinthefieldprogrammablegatearray(FPGA).Thismodelisemployedintheimplementationof20Gb/sdifferentialquadraturephase-shiftkeying(DQPSK)precoderin40Gb/spolarizationdivisionmultiplex(PolDM)DQPSKsystem.Inthecomputationprocess,thecomputationcomplexity(area)optimizationwithfan-outlimitedisachieved.Intheimplementation,770FPGAsliceregistersareutilized,whichsaveabout60%logicresourcescomparedwiththepreviousKoggeStone(KS)algorithm.

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Implementation of area optimization precoder in a 40 Gb/s PolDM-DQPSK system

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