Physical design method of MPSoC

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    摘要 Floorplan,clocknetworkandpowerplanarecrucialstepsindeepsub-micronsystem-on-chipdesign.Anoveldi-agonalfloorplanisintegratedtoenhancethedatasharingbetweendifferentcoresinsystem-on-chip.Customclocknetworkcon-taininghand-adjustedbuffersandvariableroutingrulesisconstructedtorealizebalancedsynchronization.EffectivepowerplanconsideringbothIRdropandelectromigrationachieveshighutilizationandmaintainspowerintegrityinourMediaSoC.Usingsuchmethods,deepsub-microndesignchallengesaremanagedunderafastprototypingmethodology,whichgreatlyshortensthedesigncycle.
    机构地区 不详
    出版日期 2007年04月14日(中国Betway体育网页登陆平台首次上网日期,不代表论文的发表时间)
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